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74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins ?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 ja n uary 2008 74ac299, 74act299 8-input universal shift/storage register with common parallel i/o pins features i cc and i oz reduced by 50% common parallel i/o for reduced pin count additional serial inputs and outputs for expansion four operating modes: shift left, shift right, load and store 3-state outputs for bus-oriented applications outputs source/sink 24ma act299 has ttl-compatible inputs general description the ac/act299 is an 8-bit universal shift/storage regis- ter with 3-state outputs. four modes of operation are possible: hold (store), shift left, shift right and load data. the parallel load inputs and flip-flop outputs are multi- plexed to reduce the total number of package pins. addi- tional outputs are provided for flip-flops q 0 , q 7 to allow easy serial cascading. a separate active low master reset is used to reset the register. ordering information device also available in tape and reel. specify by appending suffix letter ??to the ordering number. all packages are lead free per jedec: j-std-020b standard. order number package number package description 74ac299sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74ac299sj m20d 20-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac299mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac299pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74act299sc m20b 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide 74act299mtc mtc20 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74act299pc n20a 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 2 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins connection diagram pin description functional description the ac/act299 contains eight edge-triggered d-type flip-flops and the interstage logic necessary to perform synchronous shift left, shift right, parallel load and hold operations. the type of operation is determined by s 0 and s 1 , as shown in the truth table. all flip-flop outputs are brought out through 3-state buffers to separate i/o pins that also serve as data inputs in the parallel load mode. q 0 and q 7 are also brought out on other pins for expansion in serial shifting of longer words. a low signal on mr overrides the select and cp inputs and resets the flip-flops. all other state changes are initi- ated by the rising edge of the clock. inputs can change when the clock is in either state provided only that the recommended setup and hold times, relative to the rising edge of cp, are observed. a high signal on either oe 1 or oe 2 disables the 3-state buffers and puts the i/o pins in the high imped- ance state. in this condition the shift, hold, load and reset operations can still occur. the 3-state buffers are also disabled by high signals on both s 0 and s 1 in prepara- tion for a parallel load operation. logic symbols ieee/iec truth table h = high voltage level l = low voltage level x = immaterial = low-to-high transition pin names description cp clock pulse input ds 0 serial data input for right shift ds 7 serial data input for left shift s 0 , s 1 mode select inputs mr asynchronous master reset oe 1 , oe 2 3-state output enable inputs i/o 0 ?/o 7 pa r allel data inputs or 3-state pa r allel outputs q 0 , q 7 serial outputs inputs response mr s 1 s 0 cp lx xx asynchronous reset; q 0 ? 7 = low hhh pa r allel load; i/o n q n hlh shift right; ds 0 q 0 , q 0 q 1 , etc. hh l shift left, ds 7 q 7 , q 7 q 6 , etc. hl lx hold
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 3 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins logic diagram please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 4 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter rating v cc supply voltage ? 0.5v to + 7.0v i ik dc input diode current v i = ? 0.5v ? 20ma v i = v cc + 0.5 + 20ma v i dc input voltage ? 0.5v to v cc + 0.5v i ok dc output diode current v o = ? 0.5v ? 20ma v o = v cc + 0.5v + 20ma v o dc output voltage ? 0.5v to v cc + 0.5v i o dc output source or sink current 50ma i cc or i gnd dc v cc or ground current per output pin 50ma t stg storage temperature ? 65 c to + 150 c t j j unction temperature 140 c symbol parameter rating v cc supply voltage (unless otherwise speci?d) ac 2.0v to 6.0v act 4.5v to 5.5v v i input voltage 0v to v cc v o output voltage 0v to v cc t a operating temperature ? 40 c to + 85 c ? v / ? t minimum input edge rate, ac devices: v in from 30% to 70% of v cc , v cc @ 3.3v, 4.5v, 5.5v 125mv/ns ? v / ? t minimum input edge rate, act devices: v in from 0.8v to 2.0v, v cc @ 4.5v, 5.5v 125mv/ns
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 5 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins dc electrical characteristics for ac notes: 1. all outputs loaded; thresholds on input associated with output under test. 2. i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . 3. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = + 25 ct a = ? 40 c to + 85 c units t yp. guaranteed limits v ih minimum high level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 2.1 2.1 v 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 v il maximum low level input voltage 3.0 v out = 0.1v or v cc ?0.1v 1.5 0.9 0.9 v 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 v oh minimum high level output voltage 3.0 i out = ?0? 2.99 2.9 2.9 v 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 v in = v il or v ih , i oh = ?2ma 2.56 2.46 4.5 v in = v il or v ih , i oh = ?4ma 3.86 3.76 5.5 v in = v il or v ih , i oh = ?4ma (1) 4.86 4.76 v ol maximum low level output voltage 3.0 i out = 50? 0.002 0.1 0.1 v 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 v in = v il or v ih , i ol = 12ma 0.36 0.44 4.5 v in = v il or v ih , i ol = 24ma 0.36 0.44 5.5 v in = v il or v ih , i ol = 24ma (1) 0.36 0.44 i in (2) maximum input leakage current 5.5 v i = v cc , gnd 0.1 1.0 ? i old minimum dynamic output current (3) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ? 75 ma i cc (2) maximum quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ? i ozt maximum i/o leakage current 5.5 v i (oe) = v il , v ih ; v i = v cc , gnd; v o = v cc , gnd 0.3 3.0 ?
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 6 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins dc electrical characteristics for act notes: 4. all outputs loaded; thresholds on input associated with output under test. 5. maximum test duration 2.0ms, one output loaded at a time. symbol parameter v cc (v) conditions t a = + 25 ct a = ? 40 c to + 85 c units t yp. guaranteed limits v ih minimum high level input voltage 4.5 v out = 0.1v or v cc ? 0.1v 1.5 2.0 2.0 v 5.5 1.5 2.0 2.0 v il maximum low level input voltage 4.5 v out = 0.1v or v cc ? 0.1v 1.5 0.8 0.8 v 5.5 1.5 0.8 0.8 v oh minimum high level output voltage 4.5 i out = ? 50? 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 4.5 v in = v il or v ih , i oh = ? 24ma 0.0001 3.86 3.76 5.5 v in = v il or v ih , i oh = ? 24ma (4) 4.86 4.76 v ol maximum low level output voltage 4.5 i out = 50? 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 4.5 v in = v il or v ih , i ol = 24ma 0.36 0.44 5.5 v in = v il or v ih , i ol = 24ma (4) 0.36 0.44 i in maximum input leakage current 5.5 v i = v cc , gnd 0.1 1.0 ? i cct maximum i cc /input 5.5 v i = v cc ? 2.1v 0.6 1.5 ma i old minimum dynamic output current (5) 5.5 v old = 1.65v max. 75 ma i ohd 5.5 v ohd = 3.85v min. ? 75 ma i cc maximum quiescent supply current 5.5 v in = v cc or gnd 4.0 40.0 ? i ozt maximum i/o leakage current 5.5 v i (oe) = v il , v ih ; v i = v cc , gnd; v o = v cc , gnd 0.3 3.0 ?
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 7 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins ac electrical characteristics for ac note: 6. voltage range 3.3 is 3.3v 0.3v. voltage range 5.0 is 5.0v 0.5v. symbol parameter v cc (v) (6) t a = + 25 c, c l = 50pf t a = ? 40 c to + 85 c, c l = 50pf units min. typ. max. min. max. f max maximum input frequency 3.3 90 124 80 mhz 5.0 130 173 105 t plh propagation delay, cp to q 0 or q 7 (shift left or right) 3.3 8.5 14.0 20.5 7.0 22.0 ns 5.0 5.5 9.5 14.0 4.5 15.0 t phl propagation delay, cp to q 0 or q 7 (shift left or right) 3.3 8.5 14.5 21.5 7.0 23.0 ns 5.0 5.5 10.0 14.5 5.0 16.0 t plh propagation delay, cp to i/o n 3.3 9.0 14.5 20.5 7.5 22.5 ns 5.0 6.0 10.0 14.5 5.0 16.0 t phl propagation delay, cp to i/o n 3.3 10.0 16.0 23.0 8.5 24.5 ns 5.0 6.5 11.0 16.0 6.0 17.5 t phl propagation delay, mr to q 0 or q 7 3.3 9.0 15.5 22.5 7.5 25.0 ns 5.0 5.5 10.5 15.5 5.0 17.0 t phl propagation delay, mr to i/o n 3.3 9.0 15.0 21.5 7.5 24.0 ns 5.0 5.5 10.0 15.0 5.0 16.5 t pzh output enable time, oe to i/o n 3.3 7.0 12.0 18.0 6.0 19.5 ns 5.0 4.5 8.5 12.5 4.0 13.5 t pzl output enable time, oe to i/o n 3.3 7.0 12.5 18.0 6.0 20.5 ns 5.0 5.0 8.0 12.5 4.0 14.0 t phz output disable time, oe to i/o n 3.3 6.5 13.0 18.5 5.5 19.5 ns 5.0 3.5 9.5 14.0 3.0 15.0 t plz output disable time, oe to i/o n 3.3 5.5 11.5 17.0 4.5 19.0 ns 5.0 3.5 8.0 12.5 2.0 13.5
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 8 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins ac operating requirements for ac note: 7. voltage range 3.3 is 3.3v 0.3v. voltage range 5.0 is 5.0v 0.5v. symbol parameter v cc (v) (7) t a = + 25 c, c l = 50pf t a = ? 40 c to + 85 c, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, s 0 or s 1 to cp 3.3 3.0 8.0 8.5 ns 5.0 2.0 5.0 5.5 t h hold time, high or low, s 0 or s 1 to cp 3.3 ? 3.0 0.5 0.5 ns 5.0 ? 1.5 1.0 1.0 t s setup time, high or low, i/o n to cp 3.3 2.0 5.5 6.0 ns 5.0 1.0 3.5 4.0 t h hold time, high or low, i/o n to cp 3.3 ? 2.0 0 0 ns 5.0 ? 1.0 1.0 1.0 t s setup time, high or low, ds 0 or ds 7 to cp 3.3 2.5 6.5 7.0 ns 5.0 1.5 4.0 4.5 t h hold time, high or low, ds 0 or ds 7 to cp 3.3 ? 2.0 0 0.5 ns 5.0 ? 1.0 1.0 1.0 t w cp pulse width, low 3.3 3.5 4.5 5.0 ns 5.0 2.0 3.5 3.5 t w mr pulse width, low 3.3 4.0 4.5 5.0 ns 5.0 2.0 3.5 3.5 t rec recovery time, mr to cp 3.3 0 1.5 1.5 ns 5.0 0.5 1.5 1.5
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 9 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins ac electrical characteristics for act note 8. voltage range 5.0 is 5.0v 0.5v. ac operating requirements for act note 9. voltage range 5.0 is 5.0v 0.5v. capacitance symbol parameter v cc (v) (8) t a = + 25 c, c l = 50pf t a = ? 40 c to + 85 c, c l = 50pf units min. typ. max. min. max. f max maximum input frequency 5.0 120 170 110 mhz t plh propagation delay, cp to q 0 or q 7 (shift left or right) 5.0 4.0 8.5 12.5 3.0 14.0 ns t phl propagation delay, cp to q 0 or q 7 (shift left or right) 5.0 4.0 9.0 13.5 3.5 15.0 ns t plh propagation delay, cp to i/o n 5.0 4.5 8.5 12.5 4.5 13.5 ns t phl propagation delay, cp to i/o n 5.0 5.0 9.5 15.0 4.5 16.5 ns t phl propagation delay, mr to q 0 or q 7 5.0 4.0 14.0 15.0 4.0 18.0 ns t phl propagation delay, mr to i/o n 5.0 4.0 13.0 14.5 3.5 17.5 ns t pzh output enable time, oe to i/o n 5.0 2.5 8.0 12.0 1.5 13.0 ns t pzl output enable time, oe to i/o n 5.0 2.0 8.0 12.0 1.5 13.5 ns t phz output disable time, oe to i/o n 5.0 2.0 8.5 12.5 2.0 13.5 ns t plz output disable time, oe to i/o n 5.0 2.5 8.0 11.5 2.0 12.5 ns symbol parameter v cc (v) (9) t a = + 25 c, c l = 50pf t a = ? 40 c to + 85 c, c l = 50pf units t yp. guaranteed minimum t s setup time, high or low, s 0 or s 1 to cp 5.0 2.0 5.0 5.5 ns t h hold time, high or low, s 0 or s 1 to cp 5.0 ? 2.0 1.0 1.0 ns t s setup time, high or low, i/o n to cp 5.0 1.5 4.0 4.5 ns t h hold time, high or low, i/o n to cp 5.0 ? 1.0 1.0 1.0 ns t s setup time, high or low, ds 0 or ds 7 to cp 5.0 1.5 4.5 5.0 ns t h hold time, high or low, ds 0 or ds 7 to cp 5.0 ? 1.0 1.0 1.0 ns t w cp pulse width, high or low 5.0 2.0 4.0 4.5 ns t w mr pulse width, low 5.0 2.0 3.5 3.5 ns t rec recovery time, mr to cp 5.0 0 1.5 1.5 ns symbol parameter conditions typ. units c in input capacitance v cc = 5.0v 4.5 pf c pd po w er dissipation capacitance v cc = 5.5v 170 pf
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 10 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins physical dimensions figure 1. 20-lead small outline integrated circuit (soic), jedec ms-013, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ 0.10 c c a see detail a notes: unless otherwise specified a) this package conforms to jedec ms-013, variation ac, issue e b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. e) landpattern standard: soic127p1030x265-20l pin one indicator 0.25 1 10 b c a m 20 11 b x45 8 0 seating plane gage plane detail a scale: 2:1 seating plane land pattern recommendation f) drawing filename: mkt-m20brev3 0.65 1.27 2.25 9.50 13.00 12.60 11.43 7.60 7.40 10.65 10.00 0.51 0.35 1.27 2.65 max 0.30 0.10 0.33 0.20 0.75 0.25 (r0.10) (r0.10) 1.27 0.40 (1.40) 0.25 d) conforms to asme y14.5m-1994
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 11 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins physical dimensions (continued) figure 2. 20-lead small outline package (sop), eiaj type ii, 5.3mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 12 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins physical dimensions (continued) figure 3. 20-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 13 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins physical dimensions (continued) figure 4. 20-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pa c kage drawings are provided as a service to customers considering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawing and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package speci?ations do not expand the terms of fairchilds worldwide terms and conditions, speci?ally the warranty therein, which covers fairchild products. always visit fairchild semiconductors online packaging area for the most recent package drawings: http://www .f airchildsemi.com/pac kaging/ .001[.025] c 7 typ 7 typ 10.92 max 26.92 24.89 7.11 6.09 1.78 1.14 2.54 7.62 7.87 3.43 3.17 5.33 max 3.55 3.17 0.38 min 0.36 0.56 0.20 0.35 pin #1 notes: (0.97)
?988 fairchild semiconductor corporation www.fairchildsemi.com 74ac299, 74act299 rev. 1.4.0 14 trademarks th ef ollowing includes registered and unregistered trademarks and service marks, owned by fairchild semiconductor and/or its global s ubsidiaries, and is not intended to be an exhaustive list of all such trademarks. acex build it now coreplus crossvolt ctl current transfer logic ecospark ezswit ch * fairchild fairchild semiconductor fact quiet series fact fast fastvcore flashwriter ? fps frfet global power resource sm green fps green fps e-series gto i-lo intellimax isoplanar m egabuck mi crocoupler microfet micropak mi llerdrive mo ti on-spm optologic optopl anar pdp-spm pow er220 pow er247 poweredge power-spm po we rtrench pr ogrammable active droop qfet qs qt optoelectronics quiet series rapidconfigure smart start spm stealth s uperfet su persot -3 s upersot -6 s upersot -8 syncfet the power franchise tinyboost tinybuck tinylogic tinyopto tinypower tinypwm tinywire serdes uhc ultra f rfet unifet vcx *ezswi tch and flashwriter are trademarks of system general corporation, used under license by fairchild semiconductor. disc laimer fa i rchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fairchild does not assume any liability arising out of the application or use of any pro duct or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. these speci fications do not expand t he terms of fairchild? wo rl dw ide terms and conditions, specifically the warranty therein, which covers these products. life support policy fa i rchilds products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems wh ic h, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform wh en properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. a critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. pr oduct status definitions defi nition of terms da tasheet identification product status definition ad vance information form first production ative or in design this datasheet contains the design specifications for product development. specifications may change in any manner without notice. pr eliminary this datasheet contains preliminary data; supplementary data will be published at a later date. fairchild semiconductor reserves the right to ma ke c hanges at any time without notice to improve design. no identification needed full production this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice to improve the des i gn. obsolete not in production this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. rev. i32 74ac299, 74act299 ?8-input universal shift/storage register with common parallel i/o pins

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